A liquid crystal display device controls light transmittance through a liquid crystal material using an electric field to thereby display a picture. Toward this end, the liquid crystal display device includes a liquid crystal display panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.
The liquid crystal display panel includes a thin film transistor array substrate and a color filter array substrate disposed in opposition to each other, a liquid crystal material injected between two substrates, and a spacer for maintaining a cell gap between two substrates.
The thin film transistor array substrate consists of gate lines, data lines, thin film transistors formed as switching devices for each intersection or crossing of the gate lines and the data lines, pixel electrodes formed for each liquid crystal cell and connected to the thin film transistor, and alignment films coated thereon. The gate lines and the data lines receive signals from the driving circuits via each pad portion. The thin film transistor applies a pixel signal fed to the data line to the pixel electrode in response to a scanning signal fed to the gate line.
The color filter array substrate consists of color filters formed for each liquid crystal cell, black matrices for dividing color filters and reflecting an external light, common electrodes for commonly applying reference voltages to the liquid crystal cells, and an alignment film coated thereon.
The liquid crystal display panel is fabricated by preparing the thin film array substrate and the color filter array substrate individually, joining them and then injecting a liquid crystal between them and sealing the structure.
FIG. 1 is a plan view illustrating a related art thin film transistor array substrate, and FIG. 2 is a sectional view of the thin film transistor array substrate taken along the line I-I′ in FIG. 1.
Referring to FIG. 1 and FIG. 2, the thin film transistor array substrate includes a gate line 2 and a data line 4 provided on a lower substrate 42 in such a way as to cross each other with the gate insulating film 44 therebetween, a thin film transistor 6 provided at each crossing, and a pixel electrode 18 provided at a cell area having a crossing structure. Further, the thin film transistor array substrate includes a storage capacitor 20 (for the sake of convenience, a storage capacitor of an adjacent pixel area is shown in FIG. 1) provided at an overlapping portion of the pixel electrode 18 and the pre-stage gate line 2.
The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to the pixel electrode 16, and an active layer 14 overlying the gate electrode 8 and defining a channel between the source electrode 10 and the drain electrode 12. The active layer 14 lies under the data line 4, the source electrode 10 and the drain electrode 12, and further includes a channel portion between the source electrode 10 and the drain electrode 12. An ohmic contact layer 47 for making an ohmic contact with the data line 4, the source electrode 10 and the drain electrode 12 is further formed on the active layer 14. Herein, the active layer 14 and the ohmic contact layer 47 are referred to as a semiconductor pattern 48.
The thin film transistor 6 allows a pixel voltage signal applied to the data line 4 to be charged into the pixel electrode 18 and kept in response to a gate signal applied to the gate line 2.
The pixel electrode 18 is connected, via a first contact hole 17 passing through a protective film 50, to the drain electrode 12 of the thin film transistor 6. The pixel electrode 18 generates a potential difference with respect to a common electrode provided at an upper substrate (not shown) by the charged pixel voltage signal. This potential difference rotates liquid crystals positioned between the thin film transistor array substrate and the upper substrate owing to their dielectric anisotropy and transmits light generated by a light source (not shown) toward the upper substrate.
The storage capacitor 20 is comprised of the pre-stage gate line 2, and the pixel electrode 18 overlapped with the gate line 2 with the gate insulating film 44 and the protective film 50 therebetween. The storage capacitor 20 allows a pixel voltage charged in the pixel electrode 18 to be stably maintained until the next pixel voltage is charged.
A column spacer 15 is positioned on a gate line 2 of a TFT array substrate in order to maintain the cell gap between the TFT array substrate and the color filter array substrate
On the other hand, a dual column spacer to more reliably maintain the cell gap and prevent problems due to the liquid crystal expansion has been suggested.
FIG. 3 is a plan view showing a liquid crystal display panel having a dual column spacer (for the sake of convenience, the color filter array substrate is not shown in FIG. 3), and FIG. 4 is a sectional view of the liquid crystal display panel taken along the line II-II′ in FIG. 3.
Referring to FIG. 3 and FIG. 4, the liquid crystal display device includes a main column spacer 24 contacted with a lower alignment film 52 at an area overlapped with the storage capacitor 20, and a sub column spacer 23 positioned at an area overlapped with the gate line 2.
The main column spacer 24 is disposed at a higher position than the sub column spacer 23, thereby playing a primary role to maintain the cell gap. To this end, the storage capacitor 20 positioned below the main column spacer 24 includes a step coverage generator 54 formed from a source/drain pattern and a semiconductor pattern, unlike in FIG. 1 and FIG. 2.
Generally, the sub column spacer 23 is positioned in such a way as to be spaced with the TFT array substrate 70 to play a role to prevent problems arising from expansion of the liquid crystal. If an outside pressure is applied, the sub column spacer 23 is contacted with the TFT array substrate 70, thereby assisting a cell gap maintenance function of the main column spacer 24.
But, in such a dual spacer structure, the function of the cell gap may not be reliably performed by the step coverage generator 54 inserted to form the step coverage between the main column spacer 24 and the sub column spacer 23.
In other words, if the main column spacer 24 positioned to correspond to the step coverage generator 54 is exposed to an external pressure, the position of the main column spacer 24 may deviate from a position area of the step coverage generator 54. Accordingly, the main column spacer 24 may not perform the cell gap maintenance function. Moreover, the main column spacer 24 may separate from the color filter array substrate.
Also, the step coverage generator 54 increases a line width of the gate line 2. Thus, an aperture ratio is reduced.